1. Field of the Invention
The present invention generally relates to semiconductor devices. In particular, this present invention relates to small, thinned semiconductor device modules and methods for making them.
2. Description of the Related Art
Conventional wafer manufacturing processes include the steps of building of active devices, then placing wiring on top of the active devices. This is called a “front-end-of-line (FEOL)” method of processing a wafer and includes fabrication of active transistors and fine size interconnection wiring and vias which can scale to smaller feature sizes as technology nodes are introduced such as 90 nm, 65 nm, 45 nm, 32 nm sizes as feature size examples. Subsequently, larger wiring and vias are sequentially fabricated which is often called a “back-end-of-line (BEOL)” wiring where total FEOL and BEOL wiring levels can be on the order of 10 wiring levels. Next, the wafers would finish processing and wafer in line testing with interconnection pads or build in self test (BIST) typically using small regions for this wafer BIST. Next wafers can receive solder bumps, followed by full wafer level testing or also functional test to determine known good die, sort die by speed so that known good die can continue to be assembled onto packages after dicing, thus providing various circuit chips in a module that would have a high probability of being functionally good.
Conventional chips may have many different types of circuits incorporated into the same chip. For example, a microprocessor chip may include active logic circuits, active memory circuits such as embedded dynamic random access memory (DRAM), buses between these circuits, drivers and receiver circuits to send or receive signals off chip, and the like. These conventional chips have many different “macros” or devices. A macro may include several different circuits working together to perform a specific function. For example a “macro” may provide function such as logic circuits for computation, circuits for communication off chip while also providing electrostatic discharge protection and circuits which provide clocking function across the chip so the timing for the chip can be managed. A conventional chip may have from a few to 10's of complex macros on the same chip.
The number of process steps for manufacturing these conventional chips is a function of the number and type of circuits and/or macros that are included on the chip. For example, manufacturing of a chip with digital circuits may require a different set of processes than may be required for a chip with radio frequency type circuits. Similarly, the number of process steps increases for manufacturing a chip or wafer with integrated memory circuits in addition to logic circuits compared to a chip or wafer which has only logic circuits or only memory circuits.
The conventional approach to semiconductor chip manufacturing is to include as many of these circuits as possible on the same chip. One conventional design is called a “system-on-a-chip” (e.g., SoC or SOC) which integrates as many functions (i.e. macros) on a chip as is possible within a die size that is believed possible to yield good die from the wafer and still provide value add for the added costs incurred. These chips attempt to integrate all components of a computer or other electronic system into a single integrated circuit (chip). These chips may contain 10 to 40 macros per chip with one or more technology families such as digital, analog, mixed-signal, and/or often radio frequency functions—all on one chip (or a few chips in some cases with integration at the package level for system in package (SIP) solutions). Even when fabricating digital circuitry, added process steps would be needed for integrating two or more different chip technologies such as a processor core and memory onto the same wafer. In one sense, these integrated SOC chips are advantageous because signals between the circuits on the chip do not need to leave the chip and, instead, may only need to traverse between latches on the same chip. Further, the timing for these circuits may be tightly controlled through the use of clocking and phase lock loop type circuits.
However, as the number of circuits increases with each advancing technology node and heterogeneous technology is integrated on a single chip, the manufacturing yield may be substantially reduced due to defects and process variability and due to an increase in process steps for integration, respectively. The greater the number of circuits on a chip and finer size features such as for 45 nm, 32 nm and 22 nm mode, the higher the likelihood that a defect or process limiting variation may be present in one or more of the circuits on that chip and, thus, the overall yield for such chips is reduced. Therefore, even though conventionally hundreds of millions of circuits may be provided on a chip and have been able to achieve relatively high yield with larger feature sizes such as 180 nm, 130 nm and 90 nm with use of wafer fabrication of a specific design such as logic circuitry of memory circuitry. Even chips with high levels of homogeneous circuitry can see declines in manufacturing yield when introducing heterogeneous technology integration for older technology nodes, and even lower yields can be expected for heterogeneous integration and when using smaller technology nodes such as 45 nm and 32 nm nodes.
Additionally, as the number of circuits on a chip is increased, the cost of manufacturing and functional or quality testing for that chip also increases. A chip with a high number of circuits requires a correspondingly larger and/or complex die size. The number of circuits increases cost not only through the increased complexity but also through the increased size of the chip.
Further, as the number of circuits on a chip increases, the number of processes that is required to manufacture such a chip also increases. Thus, the cost of production of such complex chips also increases along with the number of circuits.
The number of process steps that is required to manufacture a chip is a function of the type of devices (or macros) that are being incorporated into the chip. For example, digital circuits require a different set of process steps than the process steps which might be required for radio frequency types of circuits. Similarly, the process steps for memory chips may be different than the steps required for logic chips.
Since conventionally, a system-on-a-chip approach has been taken to incorporate as many different types of devices onto a single chip as is possible, for example, it is conventionally possible to put hundreds of millions of devices upon a single chip, the manufacturing yields for these devices are typically higher when using smaller die sizes (<100 mm2) and limiting the level of heterogeneous integration compared to much larger die sizes (>300 mm2) and integration of multiple heterogeneous technologies.
Conventional chips having several different types of devices often times require hundreds of process steps to incorporate all of the different devices into the chip. For example, a conventional chip may require 300 to 400 process steps to manufacture. Adding an additional type of device to such a chip may require an additional 60 or 70 process steps overall to produce the SOC. If volumes are high, die sizes small and life cycle long, this may be a good option to achieve integration with higher yields coming after high volumes in manufacturing. However, for much shorter product life cycles, larger die sizes and lower volumes, other alternatives such as System in a Package or integration through 3D chip stacking or high bandwidth silicon packages may be applicable.
Further, some devices may include process steps that have a fairly high degree of failure and, despite the fact that the number of devices created by such steps may be very small and may, in fact, only represent a tiny percentage of devices on the chip, these process steps may be responsible for a relatively high percentage of failures, thereby significantly reducing the manufacturing yield.
Further, integration of each of these technologies into a SOC can mean longer design time and costs in order to incorporate each macro into the latest technology node for wafer fabrication even if portions of the chip could have reused prior designs or technology nodes to speed products to market.